Integrating manufacturing feedback into integrated circuit structure design

ABSTRACT

Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

BACKGROUND

The subject matter disclosed herein relates to solutions for integratingmanufacturing feedback into integrated circuit structure designs. Morespecifically, aspects of the invention provide for improving the timingclosure of a subsequent integrated circuit design by using manufacturingfeedback (e.g., parameter settings and a regression analysis) from aninitial integrated circuit design.

Modern integrated circuits (ICs) exhibit large amounts of variability intheir performance, due in part, to variations in manufacturing processesand environmental parameters. The ranges of these variations defines aprocess space, and at differing points in the process space differingtiming paths may be critical. Static timing analysis (STA) is oneapproach used to analyze, debug, and validate the time performance of anintegrated circuit chip during the design phase and in advance of actualfabrication. The timing of the chip is simulated to determine if itmeets the timing constraints to achieve timing closure and, therefore,is likely to operate properly if fabricated in accordance with thetested design.

A conventional method for determining the performance of circuitry on anintegrated circuit chip (e.g., an application specific integratedcircuit, or ASIC chip), after fabrication of the wafer, is through theuse of a Performance Scan-Ring Oscillator (PSRO), or PSRO circuit. APSRO circuit acts as a free-running ring of memory elements passing apulse, the output of which can be measured at a reserved chip outputpin. “Free-running” implies a circuit that is not clocked externally,and will run as fast as the signals can propagate through the logic ofthe circuit, i.e., limited only by the capabilities of the technologyand manufacturing process variations. The periodicity of the PSROcircuit output provides a relative indication of the circuit speed,i.e., short period means faster circuit speed. PSROs are used to gaugethe quality of the fabrication process, determine the speed of thecircuitry on various parts of the wafer, and thereby grade theperformance of individual chips on the wafer, before and after dicing.There may be more than one PSRO on a large ASIC in order to account forprocess variation within the chip.

However, the PSRO approach has some general shortcomings. For example,the PSRO approach leads to developing required coverage constraints thatare larger than necessary to form the desired chip feature. Inparticular, the PSRO approach may be insufficient in the worst-corner(WC) timing limit scenario. A corner refers to a set of processparameters/environmental conditions (or simply, parameters) that causevariations in the static timing analysis of an integrated circuit.Corners may include, for example, a “best case” corner that provides thefastest path delay between two particular nodes in a circuit path, or“worst case” corner that provides the slowest path delay between twoparticular nodes in a circuit path. Where the worst-corner (WC) orworst-case timing limit is concerned, the conventional PSRO approach maylead to an inaccurate WC timing limit due to the larger-than necessaryrequired coverage constraints.

BRIEF SUMMARY

Solutions for integrating manufacturing feedback into an integratedcircuit design are disclosed. In one embodiment, a computer-implementedmethod is disclosed including: defining an acceptable yield requirementfor a first integrated circuit product; obtaining manufacturing dataabout the first integrated circuit product; performing a regressionanalysis on data representing paths in the first integrated circuitproduct to define a plurality of parameter settings based upon theacceptable yield requirement and the manufacturing data; determining aprojection corner associated with the parameter settings for satisfyingthe acceptable yield requirement; and modifying the design of a secondintegrated circuit product based upon the projection corner and theplurality of parameter settings.

A first aspect of the invention includes a computer-implemented methodincluding the following processes: defining an acceptable yieldrequirement for a first integrated circuit product; obtainingmanufacturing data about the first integrated circuit product;performing a regression analysis on data representing paths in the firstintegrated circuit product to define a plurality of parameter settingsbased upon the acceptable yield requirement and the manufacturing data;determining a projection corner associated with the parameter settingsfor satisfying the acceptable yield requirement; and modifying a designof a second integrated circuit product based upon the projection cornerand the plurality of parameter settings.

A second aspect of the invention includes a system comprising: at leastone computing device configured to integrate manufacturing feedback intoan integrated circuit design by performing actions including: definingan acceptable yield requirement for a first integrated circuit product;obtaining manufacturing data about the first integrated circuit product;performing a regression analysis on data representing paths in the firstintegrated circuit product to define a plurality of parameter settingsbased upon the acceptable yield requirement and the manufacturing data;determining a projection corner associated with the parameter settingsfor satisfying the acceptable yield requirement; and modifying a designof a second integrated circuit product based upon the projection cornerand the plurality of parameter settings.

A third aspect of the invention includes a computer program havingprogram code embodied in at least one computer-readable storage medium,which when executed, enables a computer system to integratemanufacturing feedback into an integrated circuit design by performingactions comprising: defining an acceptable yield requirement for a firstintegrated circuit product; obtaining manufacturing data about the firstintegrated circuit product; performing a regression analysis on datarepresenting paths in the first integrated circuit product to define aplurality of parameter settings based upon the acceptable yieldrequirement and the manufacturing data; determining a projection cornerassociated with the parameter settings for satisfying the acceptableyield requirement; and modifying a design of a second integrated circuitproduct based upon the projection corner and the plurality of parametersettings.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings that depict various embodiments of the invention, in which:

FIG. 1 shows a yield curve illustrating aspects of the invention.

FIG. 2 shows a yield curve illustrating aspects of the invention.

FIG. 3 shows a yield curve illustrating aspects of the invention.

FIG. 4 shows an illustrative process flow diagram according to aspectsof the invention.

FIG. 5 shows an illustrative process flow diagram according to aspectsof the invention.

FIG. 6 shows an illustrative environment according to embodiments of theinvention.

FIG. 7 shows an illustrative process flow diagram according to aspectsof the invention.

FIG. 8 shows an illustrative process flow diagram according to aspectsof the invention.

FIG. 9 shows an illustrative process flow diagram according to aspectsof the invention.

It is noted that the drawings of the invention are not necessarily toscale. The drawings are intended to depict only typical aspects of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements between the drawings.

DETAILED DESCRIPTION

The subject matter disclosed herein relates to solutions for integratingmanufacturing feedback into integrated circuit structure designs. Morespecifically, aspects of the invention provide for improving the timingclosure of a subsequent integrated circuit design by using manufacturingfeedback (e.g., parameter settings and a regression analysis) from aninitial integrated circuit design.

As noted herein, static timing analysis (STA) is used to analyze, debug,and validate the time performance of a chip during the design phase andin advance of actual fabrication. The timing of the chip is simulated todetermine if it meets the timing constraints to achieve timing closureand, therefore, is likely to operate properly if fabricated inaccordance with the tested design.

A conventional method for determining the performance of circuitry on anintegrated circuit chip (e.g., an application specific integratedcircuit, or ASIC chip), after fabrication of the wafer, is through theuse of a Performance Scan-Ring Oscillator (PSRO). A PSRO circuit acts asa free-running ring of memory elements passing a pulse, the output ofwhich can be measured at a reserved chip output pin. “Free-running”implies a circuit that is not clocked externally, and will run as fastas the signals can propagate through the logic, i.e., limited only bythe capabilities of the technology and manufacturing process variations.The periodicity of the PSRO output provides a relative indication of thecircuit speed, i.e., short period means faster circuit speed. PSROs areused to gauge the quality of the fabrication process, determine thespeed of the circuitry on various parts of the wafer, and thereby gradethe performance of individual chips on the wafer, before and afterdicing. There may be more than one PSRO on a large ASIC in order toaccount for process variation within the chip.

However, the PSRO approach has some general shortcomings. For example,the PSRO approach leads to developing required coverage constraints thatare larger than necessary to form the desired chip feature. Inparticular, the PSRO approach may be insufficient in the worst-corner(WC) timing limit scenario. A corner refers to a set of processparameters/environmental conditions (or simply, parameters) that causevariations in the static timing analysis of an integrated circuit.Corners may include, for example, a “best case” corner that provides thefastest path delay between two particular nodes in a circuit path, or“worst case” corner that provides the slowest path delay between twoparticular nodes in a circuit path. Where the worst-corner (WC), orworst-case timing limit is concerned, the conventional PSRO approach maylead to an inaccurate WC timing limit due to the larger-than necessaryrequired coverage constraints.

In contrast to conventional PSRO-based approaches, aspects of theinvention include to following processes:

A) Define an acceptable yield requirement for an integrated circuitproduct (e.g., a chip) within a given satisfaction percentage (e.g.,95-97 percent of chips with this requirement meet test conditions). Thisacceptable yield requirement may be based both on the percentage ofproducts (e.g., chips) within a batch that meet the requirement. Theacceptable yield requirement may further be based upon the value (e.g.,monetary cost v. processing required) of a particular yield. That is,this acceptable yield may be at least partially based upon the costs ofproduction of the IC products (e.g., chips) when compared with thepercentage that may fail to meet test conditions;

B) Obtain manufacturing data about the integrated circuit product. Thismay include obtaining part analysis data and/or PSRO data aboutcomponents in the integrated circuit product (e.g., a manufacturedchip); and

C) Perform a regression analysis on data representing paths in the firstintegrated circuit product to define parameter settings which meet theseyield requirements, using the manufacturing data. This may includeperforming timing (delay) measurement on all of the different logicalpaths on the chip, and providing distribution data regarding each ofthose timing measurements for the different paths. Further, theregression analysis may include performing a Shmoo test of each pathwithin the chip. The Shmoo test, as is known in the art, is a graphicalanalysis of the actual response of a component (e.g., an integratedcircuit chip) or system varying over a range of conditions and inputs.For example, when testing an integrated circuit memory chip, voltages,temperature and refresh rates could be varied over specified ranges(where those ranges allow the chip to function as designed). Theregression analysis may be performed using both PSRO and statisticalprocess monitor (SPM) design data. The regression analysis may generateall desired parameter distributions for the chip, which enables asubsequent statistical yield analysis on those parameter distributions.In some cases, the parameter range is defined according to the yieldrequirements.

The desired parameter distributions, and the subsequently determinedyield requirements, will allow for effective timing closure in a later(or, subsequently) formed integrated circuit. As such, the manufacturingfeedback from a first chip (e.g., Chip A), may be used in improving themanufacturing of a second chip (e.g., Chip B).

One benefit of this approach is that the modification of the design fora subsequent chip need not be implemented through a re-characterizationof the chip model. That is, the fundamental SPICE (simulation programwith integrated circuit emphasis) model need not be modified accordingto this approach. This may allow the SPICE model to be applied indifferent fabrication facilities, where only minor tuning is involved tomeet the specific needs of each distinct fabrication facility.

Additionally, a general benefit of aspects disclosed herein over theconventional approaches that manufacturing feedback can help to providea more robust production model for subsequently manufactured chips. Evenfurther, as integrated circuit technology advances (e.g., from 32 nmnode to 22 nm node, etc.), aspects of the invention provide detailedfeedback to manufacturing facilities for adjusting to those advances.These benefits can also be gleaned from work with older (e.g., severalyear-old) technologies, where manufacturing facilities are able to moreaccurately control their processes (e.g., precision and variances infabrication). That is, aspects of the disclosure can improve the timingrules used in manufacturing the chip, while the sensitivities of themanufacturing process can remain relatively steady.

Turning to FIG. 1, an example worst case yield curve graph 2 (plottingchip yield v. clock frequency) and an associated parameter plot 4associated with a timing run on a first product (Prod. 1) are shown forillustrative purposes according to embodiments of the invention. Asshown, the three distinct parameter distributions 6, including P1, P2and P3 (of parameter plot 4) are projected as a yield curve 8 in theyield curve graph 2. As is known in the art, the yield curve 8 may helpoutline the yield of an integrated circuit product when accounting forthe worst-case scenario in each of the parameters (e.g., parameterdistribution curves P1, P2 and P3) and/or a combination of suchparameters.

As is further known in the art, an integrated circuit chip will performat its optimum level only when all of the slacks (e.g., timing buffers)have a value of zero, or are positive. That is, a negative slackindicates that a signal is traveling more slowly than a critical timebetween locations on the chip, while a positive slack indicates that thesignal is arriving in less than the critical designed time.

Where all of the slacks on the chip are either zero or positive, all ofthe critical timing requirements are met. This allows the chip tofunction as designed. Each slack within the chip has a sensitivity toone or more process parameters used in forming the chip. Where chips aremanufactured in sets, or bunches, some chips may be formed at the meanof a parameter distribution, while others may deviate from the mean(e.g., by a sigma value or greater, such as a worst-case corner value)across the distribution. These parameter distributions are illustratedin the parameter distribution curves P1, P2 and P3 in FIG. 1. From theseparameter distributions, it may be desirable to determine a combinationof parameters that will result in a zero (or positive) slack scenarioacross the chip. In order to determine this combination of parameters,the parameter distributions are integrated (via conventionalmathematical integration formulae) to form a yield curve, e.g., theyield curve 8 of FIG. 1. After formation of the yield curve 8, aparticular desired yield is determined (e.g., 90%, 95%, etc.), and acorresponding clock frequency for that yield can be determined.

FIG. 2 shows another example yield curve graph 12 (plotting yield v.clock frequency) including three distinct yield curves (a), (b) and (c).Yield curve (a) illustrates the yield of the full chip timing in theworst case scenario for the integrated circuit product, and yield curve(b) illustrates the yield curve from tested critical paths in theintegrated circuit product. The predetermined required yield for thisexample integrated circuit product is approximately 95%, as noted atpoint (R). When accounting for the required yield (R), the yield curveis shifted to a location between yield curve (a) and yield curve (b),illustrated by yield curve (c). Yield curve (c) illustrates the yieldwhen adjusted for critical features (e.g., closure corners). In thisexample, the clock frequency of the chip may be chosen based upon thecorresponding location of the predetermined required yield along theadjusted yield curve (c).

FIG. 3 shows another yield curve graph 22 (plotting yield v. clockfrequency) and an associated parameter plot 24 for a second (or,subsequent) product (Prod. 2) according to embodiments of the invention.The example yield curve graph 22 (and associated parameter distributions26) reflect adjusted yields and parameter distributions based uponmanufacturing feedback provided after the manufacture of a set of chipsaccording to the yield and parameters shown in FIG. 1. The yield curvegraph 22 illustrates a yield curve 28, where the worst case limits areadjusted per conventional at speed structural testing (or, ASST). Asshown, the parameter distributions 26 are adjusted (when compared withparameters 6 of FIG. 1) according to the ASST feedback (ASST pathreports). For example, parameter distribution P1 has a narrower“bell-curve” portion, parameter distribution P2 has a lower peak height,and parameter distribution P3 has been shifted with respect to theiroriginal positioning as parameter distributions 6 in FIG. 1. Asdescribed herein, after running the ASST, the parameter distributionsfor the second product (Prod. 2) can be adjusted, and the second (or,subsequent) product may be tested (e.g., via a timing analysis).Incorporating the ASST path reports into the parameter design allows thesubsequent integrated circuit product (Prod. 2) to account for themanufacturing feedback identified in the ASST process. This helps toimprove the yield on the subsequent (or, second) product.

It is understood that FIGS. 1-3 illustrate example processes ingraphical form, and may not specifically apply to all embodimentsdescribed herein. However, FIG. 3 in particular, demonstrates how ASSTfeedback can be integrated into worst case limit adjustment, therebyimproving the yield of a subsequently manufactured chip.

In one aspect, the invention includes the following processes, asoutlined in the process flow diagram depicted in FIGS. 4-5:

Process (100) Performing statistical timing closure analysis (or STATanalysis) on a first chip (chip A) using Gaussian parameterdistributions and corner limits defined by the initial integratedcircuit model;

Process (200) Measuring the static statistical timing analysis pathsperformance using a Shmoo test of each selected path within the chip;

Process (300) Testing those paths having high single-parametersensitivity (PSRO/SPM) when compared to a predetermined sensitivitythreshold, as indicated by the Shmoo test results;

Process (400) Performing a regression analysis for each chip, given theparameter values tested in process (300);

Process (500) Conducting a yield timing analysis to generate a yieldcurve for the IC product as a function of the parameter distributions.The yield requirement gives the limit for each parameter to deliver thedesired yield. This yield requirement sets the projection corner timingfor the product matching the yield;

Process (800) Determining whether the timing matches a desired capacityof the fabrication facility;

Process (900) If the timing matches the capacity of the fabricationfacility, the product (integrated circuit) specifications are updated,and the process ends;

Process (700—shown alternatively as Processes 700A or 700B between FIGS.4 and 5) If the timing does not match the desired capacity of thefabrication facility, one of two actions are taken:

Process (700A, FIG. 4) The canonical delay models may be modified byshifting and scaling the sources of variation between the timing and thecapacity of the fabrication facility; this process may be followed byreturning to process (100), performing a STAT analysis on the modified(shifted/scaled) model; or

Process (700B, FIG. 5) The fabrication plan process is updated to matchthe product (integrated circuit) timing; this process may be followed byreturning to process (200), measuring the static statistical timinganalysis paths performance using a Shmoo test of each path within thechip.

It is understood that Process (600) shown in FIGS. 4-5 may be apreliminary process, or may be updated (concurrently) based uponmodifications to the models as described with reference to Process(100)-Process (900).

In any case, as described herein, aspects of the invention may providefor solutions configured to integrate manufacturing feedback into adesign of an integrated circuit product. In one exemplary embodiment,the computer-implemented method may include: defining an acceptableyield requirement for a first integrated circuit product; performing aregression analysis on data representing paths in the first integratedcircuit product to define a plurality of parameter settings based uponthe acceptable yield requirement; determining a projection cornerassociated with the parameter settings for satisfying the acceptableyield requirement; and modifying a design of a second integrated circuitproduct based upon the projection corner and the plurality of parametersettings.

FIG. 6 depicts an illustrative environment 101 for integratingmanufacturing feedback (e.g., ASST data) into an integrated circuitstructure design according to an embodiment. To this extent, theenvironment 101 includes a computer system 102 that can perform aprocess described herein in order to integrate manufacturing feedbackinto an integrated circuit structure design. In particular, the computersystem 102 is shown as including a manufacturing feedback processingsystem 130, which makes computer system 102 operable to handleintegrating manufacturing feedback into an integrated circuit structuredesign by performing any/all of the processes described herein andimplementing any/all of the embodiments described herein.

The computer system 102 is shown including a processing component 104(e.g., one or more processors), a storage component 106 (e.g., a storagehierarchy), an input/output (I/O) component 108 (e.g., one or more I/Ointerfaces and/or devices), and a communications pathway 110. Ingeneral, the processing component 104 executes program code, such as themanufacturing feedback processing system 130, which is at leastpartially fixed in the storage component 106. While executing programcode, the processing component 104 can process data, which can result inreading and/or writing transformed data from/to the storage component106 and/or the I/O component 108 for further processing. The pathway 110provides a communications link between each of the components in thecomputer system 102. The I/O component 108 can comprise one or morehuman I/O devices, which enable a human user 112 to interact with thecomputer system 102 and/or one or more communications devices to enablea system user 112 to communicate with the computer system 102 using anytype of communications link. To this extent, the manufacturing feedbackprocessing system 130 can manage a set of interfaces (e.g., graphicaluser interface(s), application program interface, etc.) that enablehuman and/or system users 112 to interact with the manufacturingfeedback processing system 130. Further, the manufacturing feedbackprocessing system 130 can manage (e.g., store, retrieve, create,manipulate, organize, present, etc.) data, such as manufacturing data(e.g., ASST data) 142, chip data (e.g., chip dimensions, spacings,tolerances, etc.) 144 and/or chip performance data (e.g., IR droprequirements, voltages, timing requirements, etc.) 146, etc., using anysolution.

In any event, the computer system 102 can comprise one or more generalpurpose computing articles of manufacture (e.g., computing devices)capable of executing program code, such as the manufacturing feedbackprocessing system 130, installed thereon. As used herein, it isunderstood that “program code” means any collection of instructions, inany language, code or notation, that cause a computing device having aninformation processing capability to perform a particular functioneither directly or after any combination of the following: (a)conversion to another language, code or notation; (b) reproduction in adifferent material form; and/or (c) decompression. To this extent, themanufacturing feedback processing system 130 can be embodied as anycombination of system software and/or application software.

Further, the manufacturing feedback processing system 130 can beimplemented using a set of modules 132. In this case, a module 132 canenable the computer system 102 to perform a set of tasks used by themanufacturing feedback processing system 130, and can be separatelydeveloped and/or implemented apart from other portions of themanufacturing feedback processing system 130. As used herein, the term“component” means any configuration of hardware, with or withoutsoftware, which implements the functionality described in conjunctiontherewith using any solution, while the term “module” means program codethat enables the computer system 102 to implement the functionalitydescribed in conjunction therewith using any solution. When fixed in astorage component 106 of a computer system 102 that includes aprocessing component 104, a module is a substantial portion of acomponent that implements the functionality. Regardless, it isunderstood that two or more components, modules, and/or systems mayshare some/all of their respective hardware and/or software. Further, itis understood that some of the functionality discussed herein may not beimplemented or additional functionality may be included as part of thecomputer system 102.

When the computer system 102 comprises multiple computing devices, eachcomputing device may have only a portion of manufacturing feedbackprocessing system 130 fixed thereon (e.g., one or more modules 132).However, it is understood that the computer system 102 and manufacturingfeedback processing system 130 are only representative of variouspossible equivalent computer systems that may perform a processdescribed herein. To this extent, in other embodiments, thefunctionality provided by the computer system 102 and manufacturingfeedback processing system 130 can be at least partially implemented byone or more computing devices that include any combination of generaland/or specific purpose hardware with or without program code. In eachembodiment, the hardware and program code, if included, can be createdusing standard engineering and programming techniques, respectively.

Regardless, when the computer system 102 includes multiple computingdevices, the computing devices can communicate over any type ofcommunications link. Further, while performing a process describedherein, the computer system 102 can communicate with one or more othercomputer systems using any type of communications link. In either case,the communications link can comprise any combination of various types ofwired and/or wireless links; comprise any combination of one or moretypes of networks; and/or utilize any combination of various types oftransmission techniques and protocols.

The computer system 102 can obtain or provide data, such asmanufacturing data (e.g., ASST data) 142, chip data 144 and/orperformance data 146 using any solution. For example, the computersystem 102 can generate and/or be used to generate manufacturing data142, chip data 144 and/or performance data 146, retrieve manufacturingdata 142, chip data 144 and/or performance data 146, from one or moredata stores, receive manufacturing data 142, chip data 144 and/orperformance data 146, from another system, send manufacturing data 142,chip data 144 and/or performance data 146 to another system, etc.

While shown and described herein as a method and system for integratingmanufacturing feedback into an integrated circuit design, it isunderstood that aspects of the invention further provide variousalternative embodiments. For example, in one embodiment, the inventionprovides a computer program fixed in at least one computer-readablemedium, which when executed, enables a computer system to determine alithographic set point. To this extent, the computer-readable mediumincludes program code, such as the manufacturing feedback processingsystem 130 (FIG. 6), which implements some or all of the processesand/or embodiments described herein. It is understood that the term“computer-readable medium” comprises one or more of any type of tangiblemedium of expression, now known or later developed, from which a copy ofthe program code can be perceived, reproduced, or otherwise communicatedby a computing device. For example, the computer-readable medium cancomprise: one or more portable storage articles of manufacture; one ormore memory/storage components of a computing device; paper; etc.

In another embodiment, the invention provides a method of providing acopy of program code, such as the manufacturing feedback processingsystem 130 (FIG. 6), which implements some or all of a process describedherein. In this case, a computer system can process a copy of programcode that implements some or all of a process described herein togenerate and transmit, for reception at a second, distinct location, aset of data signals that has one or more of its characteristics setand/or changed in such a manner as to encode a copy of the program codein the set of data signals. Similarly, an embodiment of the inventionprovides a method of acquiring a copy of program code that implementssome or all of a process described herein, which includes a computersystem receiving the set of data signals described herein, andtranslating the set of data signals into a copy of the computer programfixed in at least one computer-readable medium. In either case, the setof data signals can be transmitted/received using any type ofcommunications link.

In still another embodiment, the invention provides a method ofgenerating a system for correcting a mask deviation. In this case, acomputer system, such as the computer system 102 (FIG. 6), can beobtained (e.g., created, maintained, made available, etc.) and one ormore components for performing a process described herein can beobtained (e.g., created, purchased, used, modified, etc.) and deployedto the computer system. To this extent, the deployment can comprise oneor more of: (1) installing program code on a computing device; (2)adding one or more computing and/or I/O devices to the computer system;(3) incorporating and/or modifying the computer system to enable it toperform a process described herein; etc.

The following figures will present examples of approaches used in theestimation of process variability across a plurality of integratedcircuit structures within a batch. These figures are only illustrative,and it is understood that additional and/or alternative processes may beintegrated with the approaches outlined herein.

FIG. 7 illustrates a schematic view of a process flow 70 according to aparameter-based approach for variability estimation. As shown, in oneembodiment, a plurality of slack values 72 for each of a first chip(Chip 1) through a final (subsequent chip, Chip M) may be used in aregression analysis (M regressions) to determine a plurality ofcorresponding parameter values 74. The corresponding parameter values 74may then be processed according to a mean and sigma (or mean/sigma)computation to generate parameter mean/sigma values (or parameter meansigmas) 76.

In the parameter-based process variation estimation approach generallyillustrated in FIG. 7, the following may be performed:

(P1)—For each chip measured, sample values of process parameters areestimated (e.g., using linear regression of the equations expressingslacks);

(P2)—Estimate mean values of global (chip-wide) process parameters,using samples values of process parameters computed for each chip, alongwith the following equation:

$\begin{matrix}{m_{j} = {\frac{1}{M}{\sum\limits_{k = 1}^{M}{\Delta \; X_{j,k}}}}} & (a)\end{matrix}$

(P3)—Estimate the sigmas (standard deviations) of the global processparameters by using sample values of local process parameters, alongwith the following equation:

$\begin{matrix}{\sigma_{j} = \sqrt{\frac{1}{M - 1}{\sum\limits_{k = 1}^{M}\left( {{\Delta \; X_{j,k}} - m_{j}} \right)^{2}}}} & (b)\end{matrix}$

In order to estimate the sample values of local process parameters, thefollowing slack equations can be utilized for a single chip number (k):

$\begin{matrix}{{{s_{1,0} + {a_{1,1}\Delta \; X_{1,k}} + {a_{1,2}\Delta \; X_{2,k}} + \cdots + {a_{1,n}\Delta \; X_{n,k}} + {a_{1,R}\Delta \; R_{1,k}}} = S_{1,k}}{{s_{2,0} + {a_{2,1}\Delta \; X_{1,k}} + {a_{2,2}\Delta \; X_{2,k}} + \cdots + {a_{2,n}\Delta \; X_{n,k}} + {a_{2,R}\Delta \; R_{2,k}}} = S_{2,k}}\ldots {{s_{N,0} + {a_{N,1}\Delta \; X_{1,k}} + {a_{N,2}\Delta \; X_{2,k}} + \cdots + {a_{N,n}\Delta \; X_{n,k}} + {a_{N,R}\Delta \; R_{N,k}}} = S_{N,k}}} & (c)\end{matrix}$

Where the following quantities are unknown:

(i) Δx_(1,k), ΔX_(2,k), . . . , ΔX_(n,k)—parameters to estimate; and

(ii) ΔR_(1,k), ΔR_(2,k), . . . , ΔR_(N,k)—errors of the regressionanalysis.

In order to determine these unknown quantities (i) and (ii), linearregression analysis may be performed, however, because the errors arepaired with the a_(i,R) coefficients, the slack equations can benormalized to account for this coefficient, transforming the slackequations to the following:

$\begin{matrix}{{{{\left( {a_{1,1}/a_{1,R}} \right)\Delta \; X_{1,k}} + {\left( {a_{1,2}/a_{1,R}} \right)\Delta \; X_{2,k}} + \cdots + {\left( {a_{1,n}/a_{1,R}} \right)\Delta \; X_{n,k}} + {\Delta \; R_{1,k}}} = {{{{\left( {S_{1,k} - s_{1,0}} \right)/{a_{1,R}\left( {a_{2,1}/a_{2,R}} \right)}}\Delta \; X_{1,k}} + {\left( {a_{2,2}/a_{2,R}} \right)\Delta \; X_{2,k}} + \cdots + {\left( {a_{2,n}/a_{2,R}} \right)\Delta \; X_{n,k}} + {\Delta \; R_{2,k}}} = {\left( {S_{2,k} - s_{2,0}} \right)/a_{2,R}}}}{{{{\ldots \left( {a_{N,1}/a_{N,R}} \right)}\Delta \; X_{1,k}} + {\left( {a_{N,2}/a_{N,R}} \right)\Delta \; X_{2,k}} + \cdots + {\left( {a_{N,n}/a_{N,R}} \right)\Delta \; X_{n,k}} + {\Delta \; R_{N,k}}} = {\left( {S_{N,k} - s_{N,0}} \right)/a_{N,R}}}} & \left( c_{T} \right)\end{matrix}$

FIG. 8 illustrates a schematic view of an alternative process flow 80according to a slack means/sigmas-based approach for variabilityestimation. As shown, in one embodiment, a plurality of slack values 82for each of a first chip (Chip 1) through a final (subsequent chip, ChipM) may be used in a mean/sigma computation to determine a plurality ofcorresponding slack means/sigma values 84. The slack means/sigma values84 may then be processed according to a regression analysis tailored formeans and sigmas to generate parameter mean/sigma values (or parametermean sigmas) 86.

In the slack means/sigma values approach generally illustrated in FIG.8, the following may be performed:

(P1)—For each timing slack (S_(i)) measured, estimate the slack mean andsigma using M samples S_(i,k) of the slack, where the slacks of eachPSRO (path) have a Gaussian distribution; This estimation may beperformed using the following formulas:

$\begin{matrix}{{\hat{S}}_{i} = {\frac{1}{M}{\sum\limits_{i = 1}^{M}{\Delta \; S_{i,k}}}}} & (a) \\{{{\sigma^{2}\left( S_{i} \right)} = {\frac{1}{M - 1}{\sum\limits_{k = 1}^{M}\left( {{\Delta \; S_{i,k}} - {\hat{S}}_{i}} \right)^{2}}}};} & (b)\end{matrix}$

(P2)—Use a regression technique for estimating the mean values of globalprocess parameters, where the regression equations are derived by takingexpected values from both sides of the slack equation; and

(P3)—Using a regression technique for estimating variances(sigma-squared) of the global process parameters, where the regressionequations are derived by computing the variances on both sides of theslack equations. This regression analysis may be aided by knowledge thatall global and uncorrelated parameters are independent.

The following slack equations can be used according to the processesnoted above:

$\begin{matrix}{{{s_{1,0} + {a_{1,1}\Delta \; X_{1}} + {a_{1,2}\Delta \; X_{2}} + \cdots + {a_{1,n}\Delta \; X_{n}} + {a_{1,R}\Delta \; R_{1}}} = S_{1}}{{s_{2,0} + {a_{2,1}\Delta \; X_{1}} + {a_{2,2}\Delta \; X_{2}} + \cdots + {a_{2,n}\Delta \; X_{n}} + {a_{2,R}\Delta \; R_{2}}} = S_{2}}\ldots {{s_{N,0} + {a_{N,1}\Delta \; X_{1}} + {a_{N,2}\Delta \; X_{2}} + \cdots + {a_{N,n}\Delta \; X_{n}} + {a_{N,R}\Delta \; R_{N}}} = S_{N}}} & (c)\end{matrix}$

The mean values may be computed from both sides of the equation,respectively:

$\begin{matrix}{{{{a_{1,1}m_{1}} + {a_{1,2}m_{2}} + \cdots + {a_{1,n}m_{n}} + {a_{1,R}\Delta \; {\hat{R}}_{1}}} = {{\hat{S}}_{1} - s_{1,0}}}{{{a_{2,1}m_{1}} + {a_{2,2}m_{2}} + \cdots + {a_{2,n}m_{n}} + {a_{2,R}\Delta \; {\hat{R}}_{2}}} = {{\hat{S}}_{2} - s_{2,0}}}\ldots {{{a_{N,1}m_{1}} + {a_{N,2}m_{2}} + \cdots + {a_{N,n}m_{n}} + {a_{N,R}\Delta \; {\hat{R}}_{N}}} = {{\hat{S}}_{N} - s_{N,0}}}} & (d)\end{matrix}$

The corresponding normalizing equations with a_(i,R) may include:

$\begin{matrix}{{{{\left( {a_{1,1}/a_{1,R}} \right)m_{1}} + {\left( {a_{1,2}/a_{1,R}} \right)m_{2}} + \cdots + {\left( {a_{1,n}/a_{1,R}} \right)m_{n}} + {\Delta \; {\hat{R}}_{1}}} = {{{{\left( {{\hat{S}}_{1} - s_{1,0}} \right)/{a_{1,R}\left( {a_{2,1}/a_{2,R}} \right)}}m_{1}} + {\left( {a_{2,2}/a_{2,R}} \right)m_{2}} + \cdots + {\left( {a_{2,n}/a_{2,R}} \right)m_{n}} + {\Delta \; {\hat{R}}_{2}}} = {\left( {{\hat{S}}_{2} - s_{2,0}} \right)/a_{2,R}}}}{{{{\ldots \left( {a_{N,1}/a_{N,R}} \right)}m_{1m}} + {\left( {a_{N,2}/a_{N,R}} \right)m_{2}} + \cdots + {\left( {a_{N,n}/a_{N,R}} \right)m_{n}} + {\Delta \; {\hat{R}}_{N}}} = {\left( {S_{N} - s_{N,0}} \right)/a_{N,R}}}} & (e)\end{matrix}$

The variance from both sides of the stack equations may be computedusing the following:

$\begin{matrix}{{{{a_{1,1}^{2}\sigma_{1}^{2}} + {a_{1,2}^{2}\sigma_{2}^{2}} + \cdots + {a_{1,n}^{2}\sigma_{n}^{2}} + {a_{1,R}^{2} \cdot {\sigma^{2}\left( {\Delta \; R_{1}} \right)}}} = {\sigma^{2}\left( S_{1} \right)}}{{{a_{2,1}^{2}\sigma_{1}^{2}} + {a_{2,2}^{2}\sigma_{2}^{2}} + \cdots + {a_{2,n}^{2}\sigma_{n}^{2}} + {a_{2,R}^{2} \cdot {\sigma^{2}\left( {\Delta \; R_{2}} \right)}}} = {\sigma^{2}\left( S_{2} \right)}}\ldots {{a_{N,1}^{2}\sigma_{1}^{2}} + {a_{N,2}^{2}\sigma_{2}^{2}} + \cdots + {a_{N,n}^{2}\sigma_{n}^{2}} + {a_{N,R}^{2} \cdot {\sigma^{2}\left( {\Delta \; R_{N}} \right)}}} = {\sigma^{2}\left( S_{N} \right)}} & (f)\end{matrix}$

The corresponding normalizing equations for the variance (sigma-squared)circumstance (a_(i,R)) may be computed using the following:

$\begin{matrix}{{\left( {a_{1,1}^{2}/a_{1,R}^{2}} \right)\sigma_{1}^{2}} + {\left( {a_{1,2}^{2}/a_{1,R}^{2}} \right)\sigma_{2}^{2}} + {\quad{\quad{\cdots + {\quad{{{\left( {a_{1,n}^{2}/a_{1,R}^{2}} \right)\sigma_{n}^{2}} + {\sigma^{2}\left( {\Delta \; R_{1}} \right)}} = {{{{\sigma^{2}\left( S_{1} \right)}\left( {a_{2,1}^{2}/a_{2,R}^{2}} \right)\sigma_{1}^{2}} + {\left( {a_{2,2}^{2}/a_{2,R}^{2}} \right)\sigma_{2}^{2}} + \cdots + {\left( {a_{2,n}^{2}/a_{2,R}^{2}} \right)\sigma_{n}^{2}} + {\sigma^{2}\left( {\Delta \; R_{2}} \right)}} = {{{{\sigma^{2}\left( S_{2} \right)}{\ldots \left( {a_{N,1}^{2}/a_{N,R}^{2}} \right)}\sigma_{1}^{2}} + {\left( {a_{N,2}^{2}/a_{N,R}^{2}} \right)\sigma_{2}^{2}} + \cdots + {\left( {a_{N,n}^{2}/a_{N,R}^{2}} \right)\sigma_{n}^{2}} + {\sigma^{2}\left( {\Delta \; R_{N}} \right)}} = {\sigma^{2}\left( S_{N} \right)}}}}}}}}} & (g)\end{matrix}$

The sigmas (σ, σ, . . . , σ_(n)) may then be computed by regression,where σ²(ΔR₁), σ²(ΔR₂), . . . , σ²(ΔR_(n)) are regression residues.These values can be used in estimating parameters of uncorrelatedvariations.

FIG. 9 illustrates a schematic view of an alternative process flow 90according to a slack means/sigmas-based approach for variabilityestimation. As shown, in one embodiment, a plurality of slack values 92for each of a first chip (Chip 1) through a final (subsequent chip, ChipM) may be processed according to likelihood function constraints 94, andsubsequently optimized using those constraints, to generate parametermean/sigma values (or parameter mean sigmas) 96.

The foregoing description of various aspects of the invention has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and obviously, many modifications and variations arepossible. Such modifications and variations that may be apparent to anindividual in the art are included within the scope of the invention asdefined by the accompanying claims.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

This written description uses examples to disclose the invention,including the best mode, and also to enable any person skilled in theart to practice the invention, including making and using any devices orsystems and performing any incorporated methods. The patentable scope ofthe invention is defined by the claims, and may include other examplesthat occur to those skilled in the art. Such other examples are intendedto be within the scope of the claims if they have structural elementsthat do not differ from the literal language of the claims, or if theyinclude equivalent structural elements with insubstantial differencesfrom the literal languages of the claims.

What is claimed is:
 1. A system comprising: at least one computingdevice configured to integrate manufacturing feedback into an integratedcircuit design by performing actions including: defining an acceptableyield requirement for a first integrated circuit product; obtainingmanufacturing data about the first integrated circuit product, whereinthe obtaining of the manufacturing data includes performing a timingmeasurement on all logical paths in the first integrated circuitproduct; performing a regression analysis on data representing thelogical paths in the first integrated circuit product to define aplurality of parameter settings based upon the acceptable yieldrequirement and the manufacturing data, wherein each of the plurality ofparameter settings includes a parameter distribution curve; determininga projection corner associated with the parameter settings forsatisfying the acceptable yield requirement, wherein the determining ofthe projection corner includes generating a yield curve for the firstintegrated circuit product as a function of a distribution of the timingmeasurement for all of the logical paths in the first integrated circuitproduct; modifying a design of a second integrated circuit product basedupon the projection corner and the plurality of parameter settings,wherein the modifying the design of the second integrated circuitproduct includes adjusting each of the parameter distribution curves ofthe plurality of parameter settings; generating a second yield curverepresenting the design of the second integrated circuit product suchthat the second yield curve accounts for each of the adjusted parameterdistribution curves; performing a statistical timing closure of themodified design of the second integrated circuit product after theadjusting of each of the parameter distribution curves, wherein theprojection corner is a worst case corner that provides the slowest pathdelay between two nodes in a circuit path; and manufacturing a physicalchip according to the design of the second integrated circuit product.2. The system of claim 1, wherein adjusting each of the parameterdistribution curves includes adjusting at least one of a width of theparameter distribution curve, a height of a peak of the parameterdistribution curve, or a lateral position of the peak of the parameterdistribution curves.
 3. The system of claim 1, wherein the acceptableyield requirement is based upon predetermined design yield.
 4. Thesystem of claim 1, wherein the at least one computing device is furtherconfigured to provide the design of the second integrated circuitproduct.
 5. The system of claim 1, wherein the regression analysisincludes at least one of: a parameter based analysis, a slack means andsigmas based analysis, or a likelihood function analysis.
 6. The systemof claim 5, wherein the regression analysis includes estimating samplevalues of the parameter settings prior to defining the plurality ofparameter settings in the parameter based analysis.
 7. The system ofclaim 1, wherein the second integrated circuit product is formedsubsequently to the first integrated circuit product.
 8. The system ofclaim 1, wherein the yield curve is adjusted for critical features byshifting the yield curve between a full chip timing yield of the firstintegrated circuit product in the worst corner scenario and a criticalpath yield of the first integrated circuit product.
 9. The system ofclaim 1, wherein the source of variation of the first integrated circuitproduct is a worst case parameter.
 10. A computer program productcomprising program code embodied in a non-transitory computer-readablemedium, which when executed, enables a computer system to integratemanufacturing feedback into an integrated circuit design by performingactions comprising: defining an acceptable yield requirement for a firstintegrated circuit product; obtaining manufacturing data about the firstintegrated circuit product, wherein the obtaining of the manufacturingdata includes performing a timing measurement on all logical paths inthe first integrated circuit product; performing a regression analysison data representing the logical paths in the first integrated circuitproduct to define a plurality of parameter settings based upon theacceptable yield requirement and the manufacturing data, wherein each ofthe plurality of parameter settings includes a parameter distributioncurve; determining a projection corner associated with the parametersettings for satisfying the acceptable yield requirement, wherein thedetermining of the projection corner includes generating a yield curvefor the first integrated circuit product as a function of a distributionof the timing measurement for all of the logical paths in the firstintegrated circuit product; modifying a design of a second integratedcircuit product based upon the projection corner and the plurality ofparameter settings, wherein the modifying the design of the secondintegrated circuit product includes adjusting each of the parameterdistribution curves of the plurality of parameter settings; generating asecond yield curve representing the design of the second integratedcircuit product such that the second yield curve accounts for each ofthe adjusted parameter distribution curves; performing a statisticaltiming closure of the modified design of the second integrated circuitproduct after the adjusting of each of the parameter distributioncurves, wherein the projection corner is a worst case corner thatprovides the slowest path delay between two nodes in a circuit path; andmanufacturing a physical chip according to the design of the secondintegrated circuit product.
 11. The computer program product of claim10, wherein adjusting each of the parameter distribution curves includesadjusting at least one of a width of the parameter distribution curve, aheight of a peak of the parameter distribution curve, or a lateralposition of the peak of the parameter distribution curves.
 12. Thecomputer program product of claim 10, wherein the acceptable yieldrequirement is based upon predetermined design yield.
 13. The computerprogram product of claim 10, further including providing the design ofthe second integrated circuit product.
 14. The computer program productof claim 10, wherein the regression analysis includes at least one of: aparameter based analysis, a slack means and sigmas based analysis, or alikelihood function analysis.
 15. The computer program product of claim14, wherein the regression analysis includes estimating sample values ofthe parameter settings prior to defining the plurality of parametersettings in the parameter based analysis.
 16. The computer programproduct of claim 10, wherein the second integrated circuit product isformed subsequently to the first integrated circuit product.
 17. Thecomputer program product of claim 10, wherein the yield curve isadjusted for critical features by shifting the yield curve between afull chip timing yield of the first integrated circuit product in theworst corner scenario and a critical path yield of the first integratedcircuit product.
 18. The computer program product of claim 10, whereinthe source of variation of the first integrated circuit product is aworst case parameter.